1. Field of the Invention
The invention relates to a semiconductor device including a MOS transistor, and a method of fabricating the same, and more particularly to a semiconductor device including a MOS transistor having semiconductor-metal compound such as silicide therein, and a method of fabricating the same.
2. Description of the Related Art
Salicide is often applied to a CMOS semiconductor device in order to reduce a parasitic resistance. In salicide, a silicide film is formed on a gate electrode and source/drain regions. Specifically, in salicide, a metal film such as a titanium (Ti) or cobalt (Co) film is formed on silicon or polysilicon, and the metal film and silicon or polysilicon are thermally annealed to thereby have the metal film reacted with silicon for forming alloy of the metal and silicon. By forming such alloy, it is possible to reduce a parasitic resistance in a desired area, ensuring a high operation speed of a semiconductor device.
Apart from salicide, shallow trench isolation (STI) is often used for accomplishing device isolation by an area smaller than an area of a conventional LOCOS oxide film. In shallow trench isolation, a trench is formed in a semiconductor substrate by etching, and then, the trench is filled with electrical insulator to thereby form an electrically insulating film by which an area where a semiconductor device is to be fabricated is electrically isolated from other areas. The thus formed electrically insulating film is deeper and thicker than a conventional LOCOS oxide film.
FIG. 1 is a cross-sectional view of a MOSFET having a salicide structure and including an electrically insulating film formed by shallow trench isolation (STI).
With reference to FIG. 1, the illustrated MOSFET is comprised of a silicon substrate 101 including a well region 102, a shallow trench isolation (STI) film 103 formed in the silicon substrate 101 for electrically isolating the well region 102 from other regions, a gate oxide film 104 formed on the well region 102, a gate electrode 105 composed of polysilicon and formed on the gate oxide film 104, a sidewall oxide film 106 formed on a sidewall of the gate electrode 105, source/drain regions 108 formed in the well region 102 around the gate electrode 105, and a metal silicide film 113 formed on the gate electrode 105 and the source/drain regions 108.
In the salicide-structured MOSFET having the shallow trench isolation film 103, the shallow trench isolation film 103 is often made thinner in a step of forming the shallow trench isolation film 103 and/or a step of carrying out wet-etching, resulting in that a recess 111 grows larger at a shoulder of the shallow trench isolation film 103. This causes a problem that if silicidation is carried out under the condition that the recess 111 is large, the metal silicide film 113 would be formed in the vicinity of the recess 111 or covering the recess 111 therewith with the result of leakage at an interface at which the source/drain regions 108 and the well region 102 make contact with each other.
FIGS. 2A to 2H are cross-sectional views of the MOSFET illustrated in FIG. 1, showing respective steps in a method of fabricating the same.
Hereinbelow is explained the above-mentioned problem with reference to FIGS. 1 and 2A to 2H.
As illustrated in FIG. 2A, a silicon nitride (SiN) film 121 is formed on the silicon substrate 101 by a thickness of about 150 nanometers by CVD. Then, the silicon nitride film 121 is formed with an opening through which the shallow trench isolation film 103 will be formed. Then, the silicon substrate 101 is etched with the silicon nitride film 121 being used as a mask, to thereby form a trench through the opening. The trench has a depth in the range of about 300 to 600 nanometers.
Then, there is formed a thermal oxidation film (not illustrated) over the silicon substrate 101 by a thickness of 3 to 50 nanometers. Then, an oxide film 122 is formed in the trench by CVD, as illustrated in FIG. 2A.
Then, an oxide film formed on the silicon nitride film 121 by CVD is removed by chemical mechanical polishing (CMP), as illustrated in FIG. 2B.
Then, as illustrated in FIG. 2C, the silicon nitride film 121 is removed by wet-etching through the use of phosphoric acid. Thus, there is formed the shallow trench isolation film 103 having a thickness in the range of about 450 to 750 nanometers by which regions in each of which a semiconductor device is fabricated are electrically isolated from one another.
Then, ions are implanted into the silicon substrate 101, and the silicon substrate 101 is thermally annealed for activating the thus implanted ions. As a result, the well region 102 is formed in the silicon substrate 101, as illustrated in FIG. 2D.
Then, an oxide film resulted from the thermal annealing by a thickness of about 3 to 50 nanometers is removed by etching. Since the shallow trench isolation film 103 is also etched at a surface thereof by the etching, the shallow trench isolation film 103 is made thinner.
Then, as illustrated in FIG. 2E, an oxide film 123 is formed entirely over the silicon substrate 101 by a thickness of 1 to 20 nanometers. Then, polysilicon 124 is deposited on the oxide film 123 by a thickness of about 200 nanometers.
Then, the polysilicon 124 and the oxide film 123 are etched into a gate electrode. Thus, as illustrated in FIG. 2F, there are formed the gate oxide film 104 and the gate electrode 105.
Then, as illustrated in FIG. 2G, an oxide film 125 having a thickness of about 10 to 20 nanometers is formed entirely over the silicon substrate 101.
Then, the oxide film 125 is etched into the sidewall 106, as illustrated in FIG. 2H.
Then, ions are implanted into the well region 102 with the gate electrode 105 and the sidewall 106 being used as a mask. Thereafter, the silicon substrate 101 is thermally annealed for activating the ions having been implanted to the well region 102. Thus, the source/drain regions 108 are formed around the gate electrode 105. A surface oxide film having been formed by the thermal annealing by a thickness of about 3 to 50 nanometers is removed by etching. In the etching of the surface oxide film, since the shallow trench isolation film 103 is also etched at a surface thereof, the shallow trench isolation film 103 is made thinner with the result of a large recess 111 at a shoulder of the shallow trench isolation film 103.
If silicidation is carried out for forming the metal silicide film 113 under the condition that the recess 111 is large at a shoulder of the shallow trench isolation film 103, the metal silicide film 113 would be formed covering the recess 111 therewith with the result of leakage at an interface at which the source/drain regions 108 and the well region 102 make contact with each other.
In order to avoid the above-mentioned problem, Japanese Patent Application Publication No. 2001-85683 has suggested a method of fabricating a semiconductor device, including the step of covering an exposed surface of the shallow trench isolation film 103 with an electrically insulating film having a resistance to wet-etching, such as a nitride film, when the shallow trench isolation film 103 has been just formed, as illustrated in FIG. 2C.
However, the shallow trench isolation film 103 is kept projected in the suggested method. Hence, the method is accompanied with a problem that if a multi-wiring structure is formed above the shallow trench isolation film 103, there would be formed a step which might break a wire or wires.
Though the MOSFET illustrated in FIG. 1 is designed to include the silicon substrate 101 and the metal silicide film 113, the above-mentioned problem in the MOSFET is found in a semiconductor device including a semiconductor substrate composed of semiconductor other than silicon, and a film composed of compound of the semiconductor and metal.
Japanese Patent Application Publication No. 3-14241 has suggested a method of fabricating a semiconductor device, including the steps of forming a trench at a surface of a silicon substrate, filling the trench with silicon oxide, thermally annealing the silicon substrate to thereby form a gate oxide film on the silicon substrate, implanting impurity into the silicon substrate with the gate oxide film being used as a mask, to thereby form an impurity-diffusion layer, removing the gate oxide film such that the impurity-diffusion layer is exposed, and forming a silicide film on the exposed impurity-diffusion layer in a selected area.
Japanese Patent Application Publication No. 3-79033 has suggested a method of fabricating a semiconductor device, including the steps of forming a trench isolation region in a semiconductor substrate, forming a silicide layer on the semiconductor substrate, and forming a diffusion layer below the silicide layer.
Japanese Patent Application Publication No. 11-340456 has suggested a semiconductor device including an electrically conductive first area formed at a surface of a semiconductor substrate, a device isolation region formed adjacent to the electrically conductive first area at a surface of the semiconductor substrate, a first protection film covering the device isolation region therewith, an electrically insulating film formed on the semiconductor substrate to cover both the electrically conductive first area and the first protection film, and having an opening through which the electrically conductive first area is exposed, an electrical conductor filling the opening therewith, and an electrically conductive second area formed on the electrically insulating film and electrically connected to the electrical conductor.